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A team of researchers led past Stanford'south Mohamed M. Sabry Aly, Subhasish Mitra, and H.-Due south. Philip Wong want to put a "skyscraper" of calculator chips in your adjacent PC. The thought is to stack application processors, retention modules, and other components one on top of the other in "a revolutionary new high-rise compages for computing," according to the Stanford News Service.

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Such an "electronic super-device" using the team's Nano-Engineered Computing Systems Technology, or N3XT, could power a computer which combines "higher speed with lower energy use [to] outperform conventional approaches by a factor of a chiliad," Wong told Stanford's news periodical.

Stacking chips has long been seen as a viable path towards building a more efficient, powerful calculating compages than the current template, which lays out and connects components on a flat lath, similar "single-story structures in a suburb," equally the researchers put information technology. Just building a "skyscraper" of fries has thus far proven difficult using silicon-based integrated circuits (ICs), which are tough to connect reliably in a stacked structure.

Sabry Aly, Mitra, Wong, and their colleagues believe they've figured out a way effectually such issues using "new nano-materials" to construct stacked computer chips in identify of traditional silicon ICs. Dubbed Nano-Engineered Computing Systems Applied science, or N3XT, the procedure involves building carbon nanotube transistors (CNTs) in a stacked organisation. The event is that instead of the relatively limited number of wires connected stacked silicon fries, a N3XT device could utilise "millions of electronic elevators that can movement more than data over shorter distances that traditional wire, using less free energy," per the researchers.

Instead of adding traditional wires to connect stacked fries in a N3XT system, communication between components is built in during the bodily process of fabrication. Since CNTs can exist created at much lower temperatures than silicon-based transistors, it'south possible to build components on summit of each other, like a processor on a retentivity module, while maintaining the integrity of those tiny "electronic elevators," the researchers noted. Silicon ICs, on the other hand, have to be made separately from each other and then stacked in "3D" arrangements later, which precludes integrating those interconnects from the commencement.

The team is besides incorporating cooling in its N3XT devices, just as traditional 2-dimensional computing architectures must have their thermals kept in bank check to forestall overheating. Stanford mechanical engineers Kenneth Goodson and Mehdi Asheghi are leading the effort to "contain thermal cooling layers" in the stacked chips, according to Stanford News Service.

The team has published its findings in a recent special issue of IEEE Computer.

I major roadblock to the adoption of N3XT or chip-stacking technologies similar it? The global semiconductor industry is massively invested in silicon-based process technology, the researchers noted.

"Shifting electronics from a low-rising to a loftier-rise architecture volition demand huge investments from industry," they were quoted every bit saying.

Even so, the incentive to exercise so is compelling, said N3XT commodity co-author Chris Re, a Stanford computer scientist and MacArthur Foundation "genius grant" winner.

"There are huge volumes of data that sit within our accomplish and are relevant to some of society's virtually pressing bug from health intendance to climate change, merely we lack the computational horsepower to bring this information to light and utilize it," Re told Stanford News Service. "Equally we all hope in the N3XT project, we may have to boost horsepower to solve some of these pressing challenges."